For the interested, here is a little writeup of what I have learned over the years ;-) about control:
(This is out of mails on linuxppc-dev)
Not really specific documentation; but some things can be learned by looking at Apple's Spec library, in the PDF datasheet about the original 7500/8500 series computers.
- The system consists of two or three pieces, not of a monolithic chip like most grafic chips today (c&t 65550 would be an example of that monolithic class, integrating bus interface, VRAM interface, control logic, and sometimes RAMDAC).
- The video subsystem resides on its own PCI-like bus, which is a 64-bit bus, clocked the same as the CPU bus (40-50 MHz), attached to the CPU bus by a bridge (named chaos). Apple calls this bus a 'vci' bus.
- control is the interface chip that attaches the VRAM to this PCI-like bus. Although it probably has other control functions, those are little known. One of those functions is defining video signal timing parameters.
- The VRAM is a dual-port DRAM (relatively slow), unlike most modern video adaptors, that use some kind of standard (single-port) modern RAM (SDRAM, SGRAM, etc...). The bus towards control (i.e. towards the CPU) is 64 bits wide; towards the RAMDAC it is 128 bits wide (at least in max VRAM configurations).
There are two banks of memory, each consisting of two 112-pin DIMM slots. Each slot can accept a 1 MB VRAM DIMM, consisting of 60- or 70-ns dual-port DRAM chips. As far as I know, each DIMM is 32 bits wide, and they need to be installed in pairs. This makes for two banks of 64-bit wide memory. According to Apple's doc, the VRAM can be accessed 128-bit wide on the RAMDAC side.
- The RAMDAC is an Apple ASIC as well, named RaDaCal, integrating the RAMDAC, CLUT and a hardware cursor device. Use and programming of the hardware cursor are yet undocumented. The known details are that the cursor needs to be drawn by the OS as some kind of sprite, in an offscreen VRAM portion reserved at the end of each scanline. The vertical position needs to be drawn at the right offset, whereas the horizontal position of the cursor is taken care of by RaDaCal, probably by setting the horizontal position info in a register. Vertical movements therefore need a redraw by the OS.
- There is probably a third chip in the system, which generates the clock signals. This can be deduced from the fact that clock parameters are set via an I2C bus off cuda, and not through either RaDaCal or control.
Obviously, all of the above information can be totally wrong ;-). If there is any Apple engineer in the audience who knows better, please do speak up!